1. Technical Field
The present invention relates in general to a system and method for a memory with combined line and word access. More particularly, the present invention relates to a system and method for a processor to perform a narrow memory access and a wide memory access to the same memory space.
2. Description of the Related Art
Circuit designers are often faced with deciding between device performance and device cost. A large portion of a device's cost corresponds with the amount of silicon area that its design requires. Since a large percentage of a device's silicon area is used for memory, a circuit designer pays particular attention to what memory cell type to use in a circuit design so that the memory meets performance requirements, but is not overly large as to unnecessarily increase device cost.
Existing art typically uses a single port memory cell type or a dual port memory cell type. The single port memory cell type is the smaller of the two and, therefore, minimizes a device's cost. However, the single port memory blocks load-store access during reload operations, thus sacrificing performance. The dual port memory cell type has the better performance of the two because a processor may write to and read from the memory simultaneously. However, the dual port memory cell type is the larger of the two, which increases device cost. A challenge found is that when a circuit designer chooses one of these memory cell types, the circuit designer typically either sacrifices performance or increases device cost.
Furthermore, static random access memory (SRAM) is typically coupled to conventional microprocessors for use as a cache. During operation, the cache is typically loaded with new data at times when the processor requires data or instructions other than those that are in the cache. As a result, the processor's program stops at a particular point because an instruction cannot be completed until the opcode or data is loaded into the SRAM and available to the processor.
What is needed, therefore, is a system and method for increased memory performance while, at the same time, minimizing the amount of silicon area that the memory requires in order to minimize a device's cost.